XPLATM ARCHITECTURE Figure l shows a high level block diagram of a 64 macrocell device implementing the XPLATM architecture. The XPLATM architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and l/0 pins.
QH88350 Price| ABSOLUTE MAXNMUM RATINGS (Tc = 250C UNLESS OTHERWISE NOTED) |
| Parameter | Symbol | Limit | Unit |
| Drain-Source Voltage | VDS | 75 | v |
| Gate-Source Voltage | VGS | 20 |
| | Tc= 25C | | 758 | A |
| Continuous Drain Current (Tj = 1750C) | Tc= 125C | ID | 66 |
| Pulsed Drain Current | IDM | 240 |
| Avalanche Current | IAR | 75 |
| Repetitive Avalanche Energyb | L= 0.1 mH | EAR | 280 | mJ |
| | Tc = 250C (T0-220AB and T0-263) | | 2500 | |
| Maximum Power Dissipationb | TA = 250C (T0_263)d | PD | 3 7 | W |
| Operating Junction and Storage Temperature Range | Tj, Tstg | -55 t0 175 | oc |
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QH88350 on stock| | | | | | IIII Input = 1.28Vp-p _ |
| | | | | | 250kHz, sine wave |
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| Yie=9ie+jbie | | | | | | | |
| VCE=10V | | | | Z | 100 | |
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| | | | | f | s | | | | |
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| | | | 25 | | | | | | |
| | | 'f 1 0 | | | | | | | |
| -l= | -o | 1m | | | | | |
| :1mA --2mA | | | | | |
| k | --4mA --7mA | | | | | | |
| | 0 | 45MHz | | | | | | |
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