| PICO PART WMHEIR1 | OUTPUT VOLTA6E voc | hVNX. LOAD CURIIEHT | OUTPUr POWEH (v a | EFF. FIJLL LOAO nPL I%lt | OUT VOLT FIIPPtE FULL LD. 11uw mv p-p | OUT VOLT TOLERMCE | V LP. REG. 10%-100% LOAPt | LWE REWUT10H | PfIICE 1-2. |
| 30AC5S | 5 | 5000 | 25 | 75 | 50 | 0 5 | 0 5 | 0 2 | 299.00 |
| 30AC12S | 12 | 2500 | 30 | 81 | 50 | 0 5 | 0 5 | 0 2 | 299 |
| 30AC15S | 15 | 2000 | 30 | 82 | 50 | 0 5 | 0 5 | 0 2 | 299 |
| 30AC24S | 24 | 1250 | 30 | 83 | 50 | 0 5 | 0 5 | 0 2 | 29e.00 |
| | | | | | | | | |
The 24LCS21 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LCS21 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LCS21 discontinues transmission (Figure 7-1).
