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ROP1014003-1P1B Datasheet

1. 1.5V operation only and with low power dissipation. 2. Powerful instruction set (129 instructions). o Binary addition, subtraction, BCD adjust, logical operation in direct and index addressing mode. o Single-bit manipulation (set, reset, decision for branch). o Various conditional branch. 0 16 working registers and manipulation. o Tablelook-up. o LCD driver data transfer. 3. Memory capacity. o ROM capacity 1152 x16 bits. o RAM capacity 80 x4 bits. 4. LCD driver output. 0 5 common outputs and 24 segment outputs (up to drive 120 LCD segments). 0 1/2 Duty, 1/3 Duty, 1/4 Duty or l/5 Duty is selected by MASK option. 0 1/2 Bias or l/3 Bias is selected by MASK option. o Single instruction to turn off all segments. o Segment output pins (SEG112) could be defined as CMOS or P_open drain output type by mask option. 5. Input/output ports. o Port IOA 4 pins, muxed with SEG24SEG27. o Port lOB 4 pins(with internal pull-low), muxed with SEG28SEG31. o Port IOC 4 pins(with internal pull-low), muxed with SEG32SEG35. IOC port had built in the input signal chattering prevention circuitry. 6. 8 level subroutine nesting. 7. Interruptfunction. o Externalfactor 2 (INT pin, Port IOC). o Internalfactors 2 (Pre-Divider, Timerl). 8. Built-in Diode for Solar Cell power regulation. 9. Built in Alarm generator.
ROP1014003-1P1B Price

Switching frequency is internally set at l.5MHz, allowing the use of small surface mount inductors and capacitors. The LTC3405A is specifically designed to work well with ceramic output capacitors, achieving very low output voltage ripple and a small PCB footprint.
ROP1014003-1P1B on stock

			-75		·1H		·1L
Parameter		Symbol	Min	Max	Min	Max	Min	Max	Unit	Note
CLK cycle time	CAS latency=3	tcc	7 5		9.0		9 0
CLK cycle time	CAS latency=2	tcc	9 0	1000	9.0	1000	12	1000	ns	1
CLK cycle time	CAS latency=l	tcc		1000		1000	25	1000	ns	1
CLK to valid output delay	CAS latency=3	tSAC		5.4		7		7
CLK to valid output delay	CAS latency=2	tSAC		7		7		8	ns	1 2
CLK to valid output delay	CAS latency=l	tSAC						20	ns	1 2
Output data hold time	CAS latency=3	tOH	2 5		2.5		2 5
Output data hold time	CAS latency=2	tOH	2 5		2.5		2 5		ns	2
Output data hold time	CAS latency=l	tOH					2 5		ns	2
CLK high pulse width		tCH	2 5		3.0		3 0		ns	3
CLK low pulse width		tCL	2 5		3.0		3 0		ns	3
Input setup time		tss	2 0		2.5		2 5		ns	3
Input hold time		tSH	1 0		1.5		1 5		ns	3
CLK to output in Low-Z		tSLZ	1		1		1		ns	2
	CAS latency=3			5 4		7		7
CLK to output in Hi-Z	CAS latency=2	tSHZ		7		7		8	ns
CLK to output in Hi-Z	CAS latency=l	tSHZ						20	ns

	mm			m¨S
DIM	MIN	TYP	MAX	MIN	TYP	MAX
A	0.80		1.10	31.5		43.3
A1	0.00		0.10	0.0		3.9
A2	0.80		1.00	31.5		39.4
b	0.15		0.30	5.9		11.8
c	0.10		0.18	3.9		7.1
D	1.80		220	70.9		86.6
E	1.80		2.40	70.9		94.5
E1	1.15		1.35	45.3		53.1
L	0.10		0.30	3.9		11.8
e		0.65			25.6
el		1.3			51.2

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