| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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ROP1016-7CR1C Datasheet N l 0 1 / Z I N I / Z d 6 N V / d O H 0 1 / I I N I / I d 8 N V / d o l l 0 1 / O I N I / O d N I O I I A I / N V / 8 d 9 N V / 9 8 d 9 N V / 9 8 d N V / t 8 d ~ N V / e 8 d Z N V / 2 8 d I N V / 1 8 d O N V / 0 8 d I O O A I S S A I I N V / Z I X 0 L N V / I I X 2 f 1 8 / H I A I M d l i / l d l I A I M d l l / 9 1 d I Y O S / 9 1 d 1 8 S / I I S / 1 d I O S / 8 1 d O Y O S / Z l d O a S / O I S / I I d ROP1016-7CR1C Price
ROP1016-7CR1C on stock Sensitivity - minimum recognizablc change in input pcr counL (bit); = volts per count or volts per LSB; i.e., a 10V full scale V/F, wit.h a 10MHz full scalc frequency, with a gaLc ume of 100ms, will output l Million counts; 10V/1 Million counts = l OyV/count sensitivity; another way to look at sensiLivity is that a 16-bit A/D has 65,535 codes (counts) or 152U,V per LSB sensitivity The 4bit DAC approximation is input to all 16 comparators. The LS tap voltages are converted to charge by capacitor C2. LS taps vary from VREF/16V to OV in 16 equal steps of VREF/256. The comparators look at the net charge on the virtual ground node to perform the LS-Flash conversion. When this conversion is complete the 4 LSB's along with the 4 MSB's are transferred to the output latches. In this way all eight outputs will change |
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