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ROX-1N7502FM Datasheet

		K6R1004CID-10
Parameter	Symbol	Min	Max	Unit
Read Cycle Time	tRC	10		ns
Address Access Time	tAA		10	ns
Chip Select to Output	tco		10	ns
Output Enable to Valid Output	tOE		5	ns
Chip Enable to Low-Z Output	tLZ	3		ns
Output Enable to Low-Z Output	tOLZ	0		ns
Chip Disable to High-Z Output	tHZ	0	5	ns
Output Disable to High-Z Output	tOHZ	0	5	ns
Output Hold from Address Change	tOH	3		ns
Chip Selection to Power Up Time	tPU	0		ns
Chip Selection to Power DownTime	tPD		10	ns

ROX-1N7502FM Price

0 5 m 5 m m 5 m 0 0 1 i 1 1 0 ( S 3 0 V _ L 1 0 A A l d d I I S O L 0 3 0 N 3 d 3 ) A - _ O N V I S 0 o A J - n d L l l 0
ROX-1N7502FM on stock

sequential, with the data from address n followed by the data from n+l. The address counter for read oper- ations increments all address bits, allowing the entire memory array contents to be serially read during one operation. At the end of the address space (address 1FFFh) the device goes into an idle state and a new read sequence must be initiated to continue reading at another address. Refer to Figure 12 for the address, acknowledge and data transfer sequence. An acknowl- edge must follow each 8-bit data transfer. After the last bit has been read, the host sends a stop condition with or without a preceding acknowledge.

T- 79:05-40 electrical characterIstics at specIfIed free-alr temperature, VCC+ = 15 V, vcc- = - 15 v

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