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RP-915S Datasheet

dual-outputISRs are designed to power DSP ICs. Both output voltages are inde- pendently adjustable with external resistors The second output may also be set to an alternate lower bus voltage with a simple pin strap. Internal power sequencing of both outputs, during both power-up and power-down, meets the requirements of most DSP chipsets.
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RP-915S on stock

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The JEDEC fuse numbers, including the User Electronic Signature All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are shown control pins. Any macrocell can be configured as registered or Il on the logic diagram on the following page. O. Up to eight registers or up to eight l/Os are possible in this mode. Dedicated input or output functions can be implemented as sub- sets of the l/0 function.

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