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Many system parameters and configu rations contribute to the dynamics of SDRAM page and bank misses. Some of these are program flow, Am5x86 CPU cache enable, Am5x86 CPU cache write-through vs. write- back, number of GP bus DMA channels active, and number of PCI masters and their burst size. For example, read accesses initiated by the Am5x86 CPU's prefetcher are typically sequential until the program flow changes as a result of a program branch, and can utilize an open SDRAM page more frequently. Am5x86 CPU write accesses tend to be directly program- dependent and not predictable and can result in SDRAM page thrashing. These dynamics change when the Am5x86 CPU's cache is enabled and when the dynamics are in write-though or write-back mode. PCI read transfers are linear, and those that request a large burst utilize an open page. Even though the dynamics associated with program flow and master accesses heavily dictate the page and bank miss rates, the user has control over some SDRAM parameters that can lessen the impact associated with system dynamics. These dynamics are as follows: