| GENERAL DATA | . The outputs lrom each slgnallnput cIrcuIt are'two ac_vottages - - |
| The 1608100 series fs a complete 4-channel multlplexed S/D | proportional Wthe' slne and cosine of the Input angla: These - |
| or R/D conVrtar contained In a sIngle nwi prafild module. Anj " | - signals are.sampled by ihe duaf.sample/hotd clrcufts at atlme . |
| synchro or resolver line-to-llne voltage between 2.5 and 130 volts | close to. the negative peaks of the referanca wawform. The |
| oan-be speoled at frequencles trom'57 Hz t0 5 KHz. | sampledoutputS ars muxe4 togetherthe carrtral processor |
| -Y - 1 Up:t0 40.lnput chariwls can be accorilriiodated byihiaddltlon: ot eerninput moduIesTIVbpaHblnaang | wWbeprocesst;d:.ewhichof-- -Wmlbe --1 - E ~ -=¨_j |
| are converted in less than 100 mlcroseconds per channel. All | Aftara conwrson cydalimtiated'Onan SCo't01.1.tnmsffion. |
| channels are simultaneously sampled an negatiw carrier peaks. | the succsssiw approximation reglster is reset, Blt l is then set |
| '. - to logic "O," all other bits remain hlgh* and the SSGT performs |
| Slgnal and referbnceputs are dlffemntlal solId sfate with higfi | the frigono§tfcomputation:8 -+isfne cos+=9sIn |
| common mode rejection and inhbrent translent protecVon^ | +: On the next dock "O" to.1~' transItion tha 6 Input to the ' |
| THEORY OF OPERATI()N The 1608100-module I8 a complete 4.channsl multlplexed S,p=-j orconverter (saelgure,4).Each:synchr0 9I=rsso{wrg connected.toseparateinput chanrid;The module contains-tr refererrce prowssor,| theraforaaIlnput 8ynchros-ortosolwrs must 8tiar6acommonretarence - 1_j=_Ij ---?|}0Iii prowssor:Isto lhe tsj9 lIlajIari{ | .regIster Is SSf Into bIt.|andt2Is sat 0Thls opqratloneandtIs sat'tulogIcr bedi When th9 dafa gQqs ;BrgI. _romwfurthetILra_-.arrSCoommand. - j_ j tii |
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The CY2509/10 is a PLL-based clock driver designed for use in dual inline memory modules. The clock driver has output frequencies of up t0 133 MHz and output to output skews of less than 250 ps. The CY2509/10 provides minimum cycle-to- cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applica- tions.
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