UV: Under voltage comparator input. This input is typically connected to a voltage divider between RTN and SOURCE to sense the magnitude of the more negative input supply. If UV is more than l.4 V above SOURCE, OV is less than l.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event of a fault, pulling UV low or OV high will reset the fault latch and allow restarting. UV can also be used as an active high logic enable input. The under-voltage comparator hysteresis is programmed by the equivalent resistance seen looking into the divider at the UV input.
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| | | | f | f | | | |
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| | | | | | l<3 | 60>l | |
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| j | | | a | lal - CONOUC7ION | ANGLE |
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| | | | jl | | J | | | | | | |
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| Item | Sym bol | Min | Max. | Unit |
| SCL clock frequency | fsa_ | | | |
| Spike tolerance on bus | tsw | 100 | ns |
| Bus free time | tBUF | | | |
| Start condition set-up time | tsu; STA | 4.7 |
| Hold time | tHD; STA | 4.0 |
| SCL "L" time | tL(M/ | 4.7 | IJs |
| SCI-H" time | tHIGH | 4.0 |
| SCL, SDA rise time | tTLH | | 1.0 |
| SCI-, SDA fall time | tTHL | 0.3 |
| Date set-up time | tsu; DAT | 250 | | |
| Date hold time | tHD; DAT | O | ns |
| SCL low to data out valid | tVD; DAT | | 3.4 | |
| Stop condition set-up time | tsu; STO | 4.0 | | US |
| t counter frequency | fi | | 1.0 | Ml- |
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