RPC25112J Datasheet| | | | | | | | | le=4U'C | | | | | | | | | | 1 | 'c= 25C | | | | | | | | | 7 | | = | 1I | )0 | 'c | | | | | | | | | | r J / f f| | | | | | | | | | | | | | | 7_ | ( | | | | | | | | | | | | | | | | | | | | | | | | | | | | #j | | | | j | | tj | | | | | | | | 1 | j | | | | | | | | | | | | | j | 1 | | | | | | | | | | | | | | | | | | | v | | | | ·3 | v | | | | | | | | | | tp = 300 ps, duty cycle < 2% IIIIIII | | | | | | | | | | | | | | | | | | | | |
RPC25112J Price Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to comple- tion, typically within 3ms. RPC25112J on stock| Pin No. 20-Lead LFCSP | Pin No. 20-Lead QSOP | Mnemonic | Description | | 18,19 17, 20 3 4 6 7 8 10 12 13 14 15 16 | 11, 20 2,19 5 6 8 9 10 12 14 15 16 17 18 | GND Vcc VIN+ VIN- DATEN SDATA CLK S~EEP BYP Vo UT- VOUT+ RAMP TXEN | Common ExternaIGround Reference. Common Positive External Supply Voltage. Noninverting Input. DC-biased to approximately Vcc/2. Should be ac-coupled with a 0.1 UF capacitor. Inverting Input. DC-biased to approximately Vcc/2. Should be ac-cou pIed with a 0.1 IJF ca pacitor. Data Enable Low Input.This port controls the 8-bit parallel data latch and shift register. A Logic O-to-l transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A l-to-0 transition inhibits the data latch (holds the previous and sim ultaneously enables the register for serial data load). Serial Data Input.This digital input allows an 8-bit serial (gain) word to be loaded into the internal register with the MSB (most significant bit) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave shift register. Logic O-to-l transition latches the data bit, and a l -to-0 transfers the data bit to the slave. This req uires the input serial data-word to be valid at or before this clock tra nsition. Low Power Sleep Mode.ln the sleep mode, the AD8324's supply current is reduced t0 30 UA.A Logic o powers down the part (high Zour state), and a Logic l powers up the part. Internal Bypass.This pin must be externally decoupled (0.1 UF capacitor). Negative Output Signal. Must be biased to Vcc. See Figu re 23. Positive Output Signal. Must be biased to Vcc. See Figure 23. External RAMP Capacitor (Optional). Logic o disables forward transmission. Logic l enables forward transmission. | | | | |
| Symbol | Parameter | Test Condition | Min | Typ. | Max | Unit | | Supply Voltage | | VBATU | Turn on threshold voltage | | 2.0 | | 4.7 | V | | IBAT | Supply current | VBAT = 14V VOUTi > OV | 4 | 10 | 15 | mA | | Output stage | | RDSON | On resistance | VBAT = 14V Tj = 250C; lout = 1A VBAT = 14V Tj = 1500C; lout = 1A | | | 500 850 | ml ml | | VCL | Clamping voltage, inductive load | lout= 0.5A | 63 | 70 | 76 | V | | IOUTi | Over current shutdown (Shutdown latch resets with pos. slope at INi) | Tj = -400C Tj = 250C Tj = 1500C | 3.0 2.5 2.2 | | 4.3 3.7 3.5 | A A A | | Output leakage current see: Open load diagnostic current | | | | | | | |
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