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1. AC characteristics apply for parallel output termination of 50 Q to VTT. 2. In bypass mode, the MPC9331 divides the input reference clock. 3. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fvco ~ FB. 4. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the Vpp (AC) specification. Violation of VCMR or VPP impacts static phase offset t(o). 5. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF . 100% aHd DCREF,MAX = 100% - DCREF,MIN 6. The MPC9331 will operate with input rise/fall times up t0 3.0 ns, but the AC characteristics, specifically t(czs), tPW,MIN DC and fMAX can only be guaranteed if tR, tF are within the specified range. 7. Data valid for fREF = 50 MHz and a PLL feedback of ~8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1). 8. Data valid for 16.67 MHz < fREF < 100 MHz and any feedback divider. tsk(0) [S] = tsk(0) [0] ~ (fREF . 3600). 9. Output duty cycle is DC = (0.5 + 500 ps . fOUT) . 100%. (e.g. the DC range at fOUT = 100 MHz is 45% < DC < 55%). 10. All outputs in ~4 divider configuration. 11. -3 dB point of PLL transfer characteristics.