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SI-7TL1441G Datasheet
i~ Packaging unit : 25 pieces For w, WW double pole and 18800 models 50 pieces l:or orher models. MORS COMPONENTS - FAX: FRANCE (+33] 63 93 19 03 BELGIUM (+32J 2 725 22 00I+11ERMANY {+49) 89 48 10 39 D-37 SWEDEN [+46} 8 626 76 16 UNITED KINGDOM (+44) 844 212986 USA [+1} 617 245 4531
SI-7TL1441G Price
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic as well as bit-handling capabilities. The instruction set consists of over 1 00 instructions: 49 one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system clock, 58% of the instructions are executed in 0.75 ffS and 40% in 1.5 ffS. Multiply and divide instructions require 3.8.
SI-7TL1441G on stock

PARAMETER FROM (INPUTI TO (OUTPUT) TEST COND~TIONS MIN TYP MA× UNIT
tPLH D Q 16 30
tPHL 14 25 rtS
tPLH11 D Q CL = 15 pF, 24 40 7 15 ns
tPHL11 RL = 400 fl. 16 30
tPLH c Q Sea Figure 1 ns
tPHL 7 15
tPLH1 c Q 16 30 ns
tPHLtl 7 15


Fully In-System Programmable and Re-programmable When Security Bit Set: - Data Verification Disabled - Data Transfer to FPSLIC not Externally Visible - Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip Erase When Security Bit Cleared: - Entire Chip Erase Performed - In-System Programming Enabled - Data Verification Enabled