| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| SI4804DYT1 | SI | 500 | 01+ |
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| SI4804DYT1 | NA | SOP8 | 00+ | 2078 |
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| SI4804DYT1 | avail | N/A | SI | 06+ |
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| SI4804DYT1 | SI | 500 | SSOP-8 |
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| SI4804DYT1 | SI | 500 | SSOP-8 |
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SI4804DYT1 Datasheet The Decoder section has two modes of operation: the Normal mode and Raw mode. In the Normal mode, the Decoder section takes 10 bits of data from the Receiver output, decodes it using 10b/8b, decodes ordered sets, checks CRC, combines four bytes into a single word output, and generates parity. In the Raw mode, the Decoder section directly combines the bytes into words, bypassing 10b/8b decoding, ordered set decoding, CRC checking, and parity generation. SI4804DYT1 Price
SI4804DYT1 on stock . Low power, pin compatible replacement for ABT func- tions . FCT-E speed at 3.2 ns . Power-off disable outputs permits live insertion . Edge-rate control circuitry for significantly improved noise characteristics . Typical output skew < 250 ps . ESD > 2000V . TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages . Industrial temperature range of -40 0C to +850C . vcc = 5v +10% C Y74FCT76827T Features: . 64 mA sink current, 32 mA source current . TypicalLP (ground bounce) <1.OV at Vcc = 5V, TA = 250d'
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