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SI4810DY-E3 Datasheet The device accepts a 622.08 MHz clock. The REFCLK input is compatible with the LVDS level and also the 3.3-V LVPECL level using ac-coupling. A ioo-l differential termination resistor is included on-chip, as well as a dc biasing circuit (3 kl to VDD and 4.5 kl to GND) for the ac-coupled case. A high quality REFCLK must be used on systems required to meet SONET/SDH standards. For non-SONET/SDH compliant systems, loose tolerances may be used. SI4810DY-E3 Price Inhibit: The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low- level ground signal to this input disables the module's output and turns off the output voltage. When the Inbibit control is active, the input current drawn by the regula- tor is significantly reduced. If the Inhibit pin is left open-circuit, the module will produce an output when- ever a valid input source is applied. Vo Adjust: A 0.1 W 1 % resistor must be directly connected between this pin and pin 7 (GND) to set the output voltage to a value higher than 0.8 V The temperature stability of the resistor should be 100 ppm/oC (or better). The set- point range for the output voltage is from 0.8 V t0 3.6 V The resistor required for a given output voltage may be calculated from the following formula. Ifleft open circuit, the output voltage will default to its lowest value. For further information on output voltage adjustment consult the related application note. SI4810DY-E3 on stock FCB (Pin 7): Forced Continuous Controllnput.Thisinputacts on both controllers and is normally used to regulate a secondary winding. Pulling this pin below 0.8V will force continuous synchronous operation on both controllers. Do not leave this pin floating. Negative Output Enable (Positive Inhibit} To configure the converter for a negative enable function, EN2 (pin 4) is left open circuit, and the system On/Off control signal is applied to ENl (pin 3). A low-level input voltage (-Vin potential) must then be applied to |