SI4824DY-T1-Q Datasheet| | Short-Circuit Current Low | VOUT Shorted to GND | q | 60 120 | mA | | | Short-Circuit Current High | VOUT Shorted to Vcc | q | 70 140 | mA | | | Output Impedance to GND | Input Code = 0 | q | 1 20 275 | | | | Output Line Regulation | Input Code = 65535, Vcc = 2.7V t0 5.5V | q | 3 | m\//V | | | | | | |
SI4824DY-T1-Q Price Positive Gain Error (AD7865-2) This is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal 2 x VREF - 3/2 LSB (AD7865 at 0 V to +5 V), VREF - 3/2 LSB (AD7865 at o V to +2.5 V) after the Unipolar Offset Error has been adjusted out. SI4824DY-T1-Q on stock| PIN | NAME | FUNCTION | | 1 | CREF1 | Reference Bias Bypass, DAC1 | | 2 | OUTIP | Positive Analog Output, DACl. Current output for the MAX5188; voltage output for the MAX5191. | | 3 | OUTllxl | Negative Analog Output, DACl. Current output for the MAX5188; voltage output for the MAX5191. | | 4 | AGND | Analog Ground | | 5 | AVDD | Analog Positive Supply, +2.7V to +3.3V | | 6 | DACEN | DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND 1: Power-up DAC with PD = DGlxID X: Enter shutdown mode with PD = DVDD (X = don't care) | | 7 | PD | Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD) 1: Enter shutdown mode | | 8 | cs | Active-Low Chip Select | | 9 | CLK | Clock Input | | 10 | N.C | Not Connected. Do not connect to this pin. | | 11 | REN | Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference. | | 12, 13, 23 | DGND | Digital Ground | | 14 | DO | Data Bit DO (LSB) | | 15-20 | D1-D6 | Data Bits Dl-D6 | | 21 | D7 | Data Bit D7 (MSB) | | 22 | DVDD | Digital Supply, +2.7V to +3.3V | | 24 | REFR | Reference Input | | 25 | REFO | Reference Output | | 26 | OUT2N | Negative Analog Output, DAC2. Current output for the MAX5188; voltage output for the MAX5191. | | 27 | OUT2P | Positive Analog Output, DAC2. Current output for the MAX5188; voltage output for the MAX5191. | | 28 | CREF2 | Reference Bias Bypass, DAC2 | | | |
The SmartACFL device set consists of a Microcontroller (MCU or MCUP) in a 128-pin TQFP, a Modem Data Pump (MDP) in a 100-pin TQFP, and a Line Side Device (LSD) (SmartDAA device) in a 32-pin TQFP. The optional Voice Codec (VC), in a 32-pin TQFP, supports voice/full-duplex speakerphone (FDSP) operation with interfaces to a microphone and speaker and to a telephone handset/headset. Figure l identifies the major hardware signal interfaces. The MCUP supports two peripheral channels, one channel for the modem and a second channel for an optional user-defined function (Function 2).
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