SI4850AKA Datasheet| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AA | nyl | j Load | Conditii | n | - | | | l"I l;IIIII[tegdeIRI I IIIllIea | | | | | | | | | | SI4850AKA Price Timing Circuits The timing block consists of a crystal oscillator, a baud rate generator, a programmable 16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from a crystal connected across the Xl/CLK and X2 inputs. If an external clock of the appropriate frequency is available, it may be connected to X1/CLK. The clock serves as the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the DUART. If an external is used instead of a crystal, X1 should be driven using a configuration similar to the one in Figure 8. SI4850AKA on stock| 1<5:0> - | | | | | PWM04 | | PWMP4- | | PWMBLK4 | PWMN4 | | · CPOUT4 | PULSE4-L | | | | | | | | | | | |
| Characteristics | Symbol | Test Condition | Min | Typ. | Max | Unit | | Gate leakage current | IGSS | VGS = +16 V, VDS = 0 | | | ±1 | uA | | Drain-Source breakdown voltage | V (BR) DSS | ID = 0.1 mA, VGS = 0 | 30 | | | V | | Drain cut-off current | IDSS | VDS = 30 V, VGS = 0 | | | 1 | uA | | Gate threshold voltage | Vth | VDS = 3 V, ID = 0.1 mA | 0 8 | | 1 5 | V | | Forward transfer admittance | YfsI | VDS = 3 V, ID = 10 mA | 25 | | | mS | | | | ID =10 mA, VGS = 4 V | | 2 2 | 4 0 | Q | | Drain-Source ON resistance | RDS (ON) | ID = 10 mA, VGS = 2.5 V | | 4 0 | 7 0 | | Input capacitance | Ciss | | | 7 8 | | pF | | Reverse transfer capacitance | C rss | VDS=3V,VGS=O,f=1 MHz | | 3 6 | | pF | | Output capacitance | coss | | 8 8 | | pF | | | Turn-on time | ton | VDD = 5 V, ID = 10 mA, | | 50 | | | | Switching time | Turn-off time | toff | VGS = 0~5 V | | 180 | | ns | | | | | | | | | |