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SI5402DC-T1-Q Datasheet

Soldering and Defluxing: This module is designed for manual soldering. The leads must be soldered after the module is screwed onto the heat sink. The soldering temperature must be lower than 2600C for a maximum of 10 seconds, or lower than 3500C for a maximum of three seconds. Ethyl Alcohol is recommend for removing flux. Trichlorethylene solvents must not be used (they may cause bubbles in the coating of the transistor chips which can lift off the bond wires).
SI5402DC-T1-Q Price

Parameter	Conditions	Minimum	Typical	Maximum	Units
ABSOLUTE MAXIMUM RATINGS (note l)
Supply voltage, VD D	Referenced to GND	-0.5		7	V
Inputs and Clock Outputs	Referenced to GND	-0.5		VDD+0.5	v
Electrostatic Discharge	MIL-STD-883	2000			v
Ambient Operating Temperature		0		70	oC
Soldering Temperature	Max of 10 seconds			260	oC
Junction temperature				150	oC
Storage temperature		-65		150	oC
DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Operating Voltage, VDD		3.13		5.50	V
Input High Voltage, VIH, CLKIN pin only		VD D/2+1	VDD/2		v
Input Low Voltage, VIL, CLKIN pin only			VDD/2	VDD/2-1	v
Input High Voltage, VIH		2			v
Input Low Voltage, VIL				0.8	v
Output High Voltage, VOH	IOH=-25mA	2.4			v
O utput Low Voltage, VO L	IO L=25mA			0.4	v
Output High Voltage, VO H, CMO S level	IO H=-8mA	VDD -0.4			v
Operating Suppl Current,IDD (Note 2)	No Load, Sl=l, SO=O		25		mA
Operating Suppl Current,IDD (Note 3)	No Load, Sl=l, SO=O		74		mA
Short Circuit Current	Each output		50		mA
Input Capacitance	SO, Sl, FBIN		7		pF
AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Input Clock Frequency	See table on page 2	5		80	MHz
O utput Clock Frequency	See table on page 2	5		160	MHz
Output Clock Rise Time, CL=30pF	0.8 t0 2.OV			1.5	ns
Output Clock Fall Time, CL=30pF	2.0 t0 0.8V			1.5	ns
Output Clock Duty Cycle, VDD=3.3V	At VDD/2	40	50	60	%
Device to D evice Skew, equally loaded	rising edges at VDD/2			700	ps
O utput to O utput Skew, equally loaded	rising edges at VDD/2			250	ps
Input to Output Skew, FBIN to CLK8	rising edges at VDD/2			350	ps
Maximum Absolute Jitter			300		ps
Cycle to Cycle Jitter, 30pF loads				500	ps

SI5402DC-T1-Q on stock

	Parameter	Max	U nits
ID@ Te= 250C	Continuous Drain Current, VGS @ 10 V	7.7	A
ID @ Te = 1000C	Continuous Drain Current, VGs @ 10 v	4 9
IDM	Pulsed Drain Current	31
PO@ Te= 250C	Power Dissipation	25
PD@ TA= 250C	Power Dissipation (PCB Mount)"	2.5	W
	Linear Derating Factor	0 20
	Linear Derating Factor (PCB Mount)"	0 020	w/oc
VGS	Gate-to-Source Voltage	±20	V
EAS	Single Pulse Avalanche Energy	47	mJ
dv/dt	Peak Diode Recovery dv/dt	4 5	V/ns
TJ, TSTG	Junction and Storage Temperature Range	- 55 to +150
	Soldering Temperature, for 10 seconds	260 (1.6mm from case)	oc

Double-poly NMOS capacitors are extremely stable over tem- perature. However, the impedances of parasitic capacitances (which affect clock feedthrough and power supply ripple rejec- tion noise contributions) will vary in amplitude as a function of clock frequency or the frequency content of the power supply ripple. Filtering of the power supply lines wili minimize ripple noise and will help protect the device from random power line transients, including power-up spikes.

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