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SI9105DWSO-16L SI9105DWSO-16L SI9105DWSO16L Datasheet
DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and tha the final judgement concerning selection and specifications is the buyer's and lhal in furnishing engineering and lechnical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such products
SI9105DWSO-16L SI9105DWSO-16L SI9105DWSO16L Price

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
9fs Forward transconductance VDS = 25 V; ID = 25 A 1 2 25 S
Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 75 A; VDD= 24 V; VGS = 10 V 84 14 28 nC nC nC
Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f= 1 MHz 4000 1150 450 pF pF pF
td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 25 A VGS = 10 V; RG = s I Resistive load 40 70 1 00 50 50 1 05 140 70 ns ns ns ns
Ld Ld Ls Internal drain inductance Internal drain inductance Internal source inductance Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad 3.5 4.5 7.5 nH nH nH


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RATINGS SYMBOL 1AIG 1A2G 1A3G 1A4G 1A5G 1A6G 1A7G U NITS
Maximum Recurrent Peak Reverse Voltage VRRM 50 100 200 400 600 800 1000 Volts
Maximum RMS Voltage VRMS 35 70 140 280 420 560 700 Volts
Maximum DC Blocking Voltage VDC 50 100 200 400 600 800 1000 Volts
Maximum Average Forward Rectified Current at TA : 250C IO 1 0 Amps
Peak Forward Surge Current 8.3 ms single half sine-wave superimposed on rated load (JEDEC method) 25 Amps
Typical Junction Capacitance (Note) cJ 15 pF
Typical Thermal Resistance RejA 60 oc/w
Operating and Storage Temperature Range TJ, TSTG -65 to +175 Dc


J L
I Product INumber 1 93HC46: 1K Temper Blank = I = Indu A = Autc
E = Extc
Package P = PDIP S = SOIC (JEDEC) J = SOIC (JEDEC) U = TSSOP