| PARAMETER | | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
| Supply Current - Active | | | | 110.0 | 150 | mA |
| Supply Current - Standby | | | | 10.0 | 15 | mA |
| Digital Inputs |
| High Level Input Voltage | VIH | | 0.8*DVDD | | | V |
| Low Level Input Voltage | VIL | | | | 0.2*DVDD | V |
| High Level Input Current | IIH | | | | 1.0 | |
| Low Level Input Current | IIL | | | | 1.0 | cqA |
| Input Capacitance | | | | 10.0 | | pF |
| Digital Outputs |
| High Level Output Voltage | VOH | IOH=1.OmA | DVDD-0.75 | | | V |
| Voltage output range | VOL | IOL=1.OmA | | | DG ND+0.75 | V |
| High Impedance Output Current | ioz | | | | 1,0 | |
| Input Multiplexer |
| Channel to Channel Gain Matching | | | | 0.5 | | % |
| Input Video Set-up Time | tvsu | | 10 | | | ns |
| Input Video Hold Time | tVH | | 25 | | | ns |
| Reset Video Set-up Time | tRSU | CDS Mode only | 10 | | | ns |
| Reset Video Hold Time | tRH | CDS Mode only | 25 | | | ns |
| Reference String |
| Reference Voltage - Top | VRT | VRU = 5.00 V, VRL = O.OOV | 3.465 | 3.5 | 3.535 | V |
| Reference Voltage - Bottom | VRB | VRU = 5.00 V, VRL = O.OOV | 1.465 | 1.5 | 1.535 | V |
| DAC Reference Voltage | VMID | VRU = 5.00 V, VRL = O.OOV | 2.475 | 2.5 | 2.525 | V |
| R.L.C. Switch Impedence | | | | 200 | | Ohms |
| Reset Level Clamp Options | VRLC | VRU = 5.00 V, VRL = O.OOV | 1.425 | 1.5 | 1.575 | V |
| Voltage set by user | 2.375 | 2.5 | 2.625 | V |
| configuration - Table 7 | 3.325 | 3.5 | 3.675 | V |
| Impedance VRT to VRB | | | 490 | 700 | 910 | Ohms |
| Impedance VRU to VRL | | | 1 190 | 1700 | 2210 | Ohms |
| 8-bit DACs |
| Resolution | | | 8 | | | Bits |
| Zero Code Voltage | | | VDAC -10 | | VDAC+10 | mV |
| Full Scale Voltage Error | | | 0 | | 10 | mV |
| Differential Non Linearity | DNL | | | 0.1 | 1 | LSB |
| Integral Non Linearity | INL | | | 0.4 | 1 | LSB |
| | | | | | |
Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See for output drive characteristics of the XPLA3 family. 3. See for typical values. 4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to Vcc or ground. This parameter guaranteed by design and characterization, not testing. 5. Typical values, not tested.
An external capacitor on the TIMER pin sets the total charge time. After a time-out occurs, the charging will be terminated immediately and the CHRG pin is forced to a high impedance state. To restart the charge cycle, simply remove the input voltage and reapply it, or float the PROG pin momentarily.
