| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
SI9241EYT1 Datasheet
SI9241EYT1 Price Data Input. During data input the ST24/25x16 samples the SDA bus signal on the rising edge of the clock SCL. Note that for correct device opera- tion the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. SI9241EYT1 on stock
NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of 5 ns maximum. For Xl/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. 3. Typical values are at +25 YC, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7 k I to Vcc. 5. All outputs are disconnected. Inputs are switching between CMOS levels of Vcc - 0.2 V and Vss + 0.2 V. |