SI9432DY Datasheet A single data word write cycle is shown in Figure 4. The cycle is initiated by the high-to-low transition of the CS_N line. 32 SCK pulses clock the instruction and the data into the MOSI line. Instructions and data are clocked in MSB first. The first 16 bits are the instruction; the second 16 bits are the data word. There are two possible single data word write cycle instructions: register write and memory write. The formats for these instructions are shown in Figure 5 and Figure 6. SI9432DY Price| TA = 25IC CFLY = l | | | | | | | | | | | | VIN - 3V | | | | | = 2.7V | j | | | lj | | | | | | |
SI9432DY on stock| 1 | Rev : C Amendment:/0 Issue Date: March 2003 | | |
| PIN NUMBER | SYMBOL | NAME AND FUNC110N | | 1 | OEAB | Output enable input, A side to B side (active-High) | | 6, 7, 8, 9 | AO -A7 | Data inputs/outputs (A side) | | 18, 17, 16, 15, 14, 13, 12, 11 | BO - B7 | Data inpuWoutputs (B side) | | 19 | OEBA | Output enable input, B side to A side (active-Low) | | 10 | GND | Ground (OV) | | 20 | vcc | Positive supply voltage | | | |
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