| SYMBOL | PIN NUMBER | TYPE | DESCRIPTION |
| | 71,70,69,68,67 64,63,62,61,60 57,56 | (3.3V) | |
| IICDIV[1 :0] | 21,22 | l | IICDIV[1:0] allow to select the frequency of the 12C internal system clock, depending on the crystal frequency. Internal 12C clock is a division of XIN by 2'''D" and must be between 6 and 20 MHz. |
| SADDR[1:0] | 23,24 | l | SADDR[1:0] are the 2 LSBs of the 12C address of the VES1820X. The MSBs are internally set t0 00010. Therefore the complete 12C address of the VES1820X is (MSB to LSB) : 0, 0, 0, 1, 0, SADDR[1], SADDR[O]. |
| SDA | 26 | I/O (5V) | SDA is a bidirectional signal. It is the serial input/output of the 12C internal block. A pull-up resistor (typically 4.7 kl ) must be connected between SDA and VDD for proper operation (Open Drain output). |
| SCL | 25 | l | 12C clock input. SCL should nominally be a square wave with a maximum frequency of 400KHz. SCL is generated by the system 12C master. |
| TEST | 1 9 | l | Test input pin. For normal operation of the VES1820X, TEST must be grounded. |
| TRST | 35 | l | Test ReSeT. This active low input signal is used to reset the TAP controller when in boundary scan mode. In normal mode of operation TRST must be set low. |
| TDO | 37 | O (5V) | Test Data Out. This is the serial Test output pin used in boundary scan mode. Serial Data are provided on the falling edge of TCK. |
| TCK | 33 | l | Test ClocK : an independant clock used to drive the TAP controller when in boundary scan mode. In normal mode of operation, TCK must be grounded. |
| TDI | 34 | l | Test Data In. The serial input for Test data and instruction when in boundary scan mode. In normal mode of operation, TDI must be set to GND. |
| TMS | 36 | l | Test Mode Select. This input signal provides the logic levels needed to change the TAP controller from state to state. In normal mode of operation, TMS must be set to VDD. |
| CTRL1 | 31 | I/O (5V) | CTRLl is equivalent to SDA I/O of VES1820X but can be tri-stated by 12C programmation. It is actually the output of a switch controlled by parameter BYPIIC of register TEST (index OF16). CTRLl is open drain output, and therefore requires an external pull up resistor. |
| CTRL2 | 32 | O (5V) | CTRL2 can be configured to be a control line output or to output SCL input. This is controlled by parameter BYPIIC of register TEST (index OF16). CTRL2 is an open drain output and therefore requires an external pull up resistor. |
| 1T | 38 | O (5V) | InTerrupt line. This active low output interrupt line can be configured by the 12C interface. See registers ITsel (index 3216) and ITstat (index 33ia). IT is an open drain output and therefore requires an external pull up resistor. |
| FEL | 39 | O (5V) | By default FEL is a front-end lock indicator. In this case FEL is an open drain output and therefore requires an external pull up resistor. But FEL can also be configured to output a PWM signal, which value can be programmed through the 12C interface (see register PWMREF, index 34). |
| VIP | 92 | l | Positive input to the ND converter. This pin is DC biased to half- supply through an internal resistor divider (2 x 10kl resistors). In order to remain in the range of the ADC, the voltage dierence between pins VIP and VIM should be between -0.5 and 0.5 volts. |
| VIM | g1 | l | Negative input to the /VD converter. This pin is DC biased to half- |
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