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SIC-01-064-361 TP Datasheet

CHARACTERISTIC	SYMBOL	MIN	TYP	MAX	UNIT	TEST CONDITIONS
Drain Current	IDD	40	55	80	mA	RF OFF
Gate Current	IGG		1	2	mA	RF OFF
Power Gain	Gp	12			dB	f = 0.05 t0 2 GHz
Power Gain	Gp	10			dB	f=2 t0 3 GHz
Gain Flatness	AGp		+1 5	+2 0	dB	f = 0.05 t0 2 GHz
Gain Flatness	AGp		+2 0	+3 0	dB	f = 0.05 t0 3 GHz
Noise Figure	NF		4 0	4.5	dB	f = 0.05 t0 2 GHz
Noise Figure	NF		4 5	5O	dB	f=2 t0 3 GHz
Input Return Loss	RLin	6	10		dB	f = 0.05 t0 1 GHz
Input Return Loss	RLin	10	14		dB	f=1 t0 2 GHz
Input Return Loss	RLin	6	10		dB	f=2 t0 3 GHz
Output Return Loss	RLout	10	16		dB
Isolation	ISOL	30	40		dB	f = 0.05 t0 3 GHz
Output Power at l dB Gain Compression Point	Po (1dB)	+7	+9		dBm	f = 0.05 t0 3 GHz

SIC-01-064-361 TP Price

PRODUCT FEATURES I ENHANCED 8 BIT CPU WITH EXTENDED ADDRESSING MODES 1 126 KBYTES USER ROM WITH PARTITIONING i 4 KBYTES USER RAM WITH PARTITIONING 1 34 KBYTES USER EEPROM WITH PARTITIONING including 128 BYTES USER and ST OTP AREA: - Highly reliable CMOS EEPROM submicron technology - Error Correction Code for single bit fail correction within a byte - 10 year data retention - 500,000 Erase/Write cycles endurance - 1 t0 64 bytes Erase or Program in l.5 ms I SECURITY FIREWALLS FOR MEMORIES, and DES ACCELERATOR. I VERY HIGH SECURITY FEATURES INCLUDING EEPROM FLASH PROGRAMMING AND CLOCK MANAGEMENT. 1 3x8 BIT TIMERS WITH INTERRUPT CAPABILITY I HARDWARE DES ACCELERATOR WITH LIBRARY SUPPORT FOR SYMMETRICAL ALGORITHMS: - DES, triple DES, DESX computations and CBC chaining mode... I IS0 3309 CRC CALCULATION BLOCK I FIPS 140-2 COMPLIANT RANDOM NUMBER GENERATOR WITH TWO GUN REGISTERS (Generators of Unpredictable Number)
SIC-01-064-361 TP on stock

Page Write The CAT25C33/65 features page write capability. After the first initial byte the host may continue to write up t0 64 bytes of data to the CAT25C33/65. After each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only restriction is that the 64 bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. The CAT25C33/65 is automatically returned to the write disable state at the completion ofthe write cycle. Figure 8 illustrates the page write sequence.

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