| SYMBOL | PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT |
| INPUT CE (REFERENCED TO DGND) SEE TABLE 2 |
| VIL | LOW level input voltage | | 0 | | 0.8 | V |
| VIH | HIGH level input voltage | | 2.0 | | VCCD | V |
| IIL | LOW level input current | VIL=0.4 V | -400 | | | |
| IIH | HIGH level input current | VIH= 2.7 V | | | 20 | |
| Reference resistance |
| Rref | reference resistance | VRT to VRB | | 200 | | l |
| Outputs |
| DIGITAL OUTPUTS D7 TO DO (REFERENCED TO DGND) |
| VOL | LOW level output voltage | 10 = 1 mA; Tamb = 0 to +85 IC | 0 | | 0.4 | V |
| 10 = 1 mA; Tamb = 0 to -40 IC | | | 0.6 | V |
| VOH | HIGH level output voltage | 10= -0.4 mA | 2.7 | | VCCD | V |
| 10z | output current in 3-state mode | 0.4 V < Vo < VCCD | -20 | | +20 | |
| Switching characteristics |
| CLOCK INPUT CLK (NOTE l; SEE FIG.15) |
| fclk(max) | maximum clock frequency TDF8704T/2 TDF8704T/4 TDF8704T/5 | | 20 40 50 | | | MHz MHz MHz |
| tCPH | clock pulse width HIGH | | 7 | | | ns |
| tCPL | clock pulse width LOW | | 7 | | | ns |
| Analog signal processing |
| LINEARITY |
| ILE | DC integral linearity error | | | +0.4 | +1.0 | LSB |
| DLE | DC differential linearity error | | | ±0.2 | +0.5 | LSB |
| AILE | AC integral linearity error | note 2 | | | +l.0 | LSB |
| BANDWIDTH (fclk = 40 MHz) |
| B | -0.5 dB analog bandwidth | full-scale sine wave | | 12 | | MHz |
| (note 3) | 75% full-scale sine wave | | 16 | | MHz |
| tSTLH | analog input settling time LOW-to-HIGH | full-scale square wave; Fig.8; note 4 | | 2.5 | 3.5 | ns |
| tSTHL | analog input settling time HIGH-to-LOW | full-scale square wave; Fig.8; note 4 | | 3.0 | 4.0 | ns |
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