| PARAMETER | TEST CONDITIONS | MIN TYP MAX | UNIT |
| Analog Output |
| Coarse gain linearity (INL) | LSB = 1/10tr, of full scale | +0.016 | LSB |
| Fine gain linearity (INL) | | +3 | LSB |
| Offset error | Mid-code offset | 0.003 | %FSR |
| | Without internal reference | 0.7 | |
| Gain error | With internal reference | 0.7 | %FSR |
| Gain mismatch | With internal reference, dual DAC, SSB mode | -2 2 | %FSR |
| Full-scale output current(3) | | 2 20 | mA |
| Output compliance range(4) | IOUTFS = 20 mA | AVDD - 0.5 AVDD + 0.5 | V |
| Output resistance | | 300 | kl |
| Output capacitance | | 5 | pF |
| Reference Output |
| Reference voltage | | 1.14 1.2 1 26 | V |
| Reference output current(5) | | 100 | nA |
| Reference Input |
| VEXTIO Input voltage range | | O1 1 25 | V |
| Input resistance | | 1 | Ml |
| Small-signal bandwidth | | 2.5 | kHz |
| Input capacitance | | 100 | pF |
| Temperature Coefficients |
| Offset d rift | | +3 | ppm of FSR/IC |
| | Without internal reference | +15 | ppm of |
| Gain drift | With internal reference | +40 | FSR/IC |
| Reference voltage drift | | +25 | ppmnC |
| Power Supply |
| AVDD Analog supply voltage | | 3 3.33.6 | V |
| DVDD Digital supply voltage | | 1.65 1.8 1 95 | V |
| CLKVDD Clock supply voltage | | 3 3.33.6 | V |
| IOVDD l/0 supply voltage | | 1.65 3.6 | V |
| PLLVDD PLL supply voltage | | 3 3.33.6 | V |
| | Single (quad) DAC mode; including output current through load resistor, mode 7 | 30 | |
| IAVDD Analog supply current | Dual DAC mode; including output current through load resistor, mode 11 | 55 | mA |
| IDVDD Digital supply current | | 242 | mA |
| ICLKVDD Clock supply current | fDATA = 125 MSPS, SSB mode, | 10 | mA |
| IPLLVDD PLL supply current | Fupdate = 500 MSPS, 40-MHz IF | 28 | mA |
| IIOVDD lo supply current | <3 | mA |
| | | |
