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suppliers of SIE503.3LT and PDF data of SIE503.3LT

Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  
SIE503.3LT MORION    07+    14 
    HK KK International Co., Ltd
  • Contact:yang
  • Tel:86-755-29055076
  • Fax:
  • Email: sales1@kkpart.com


SIE503.3LT POWER-ONE    2007  original in stock  18 
    EAST WIN TECHNOLOGY(HK)ELECTRO..
  • Contact:Philip chen
  • Tel:852-27592923/0755-83226762/88820516
  • Fax:852-27592926/0755-82518619
  • Email: philip.chen@eastwinelec.com


SIE503.3LT POWER-ONE  PCB安装DC-DC  0747  原装特价四天货期  7800 
    Shen Zhen JinShengDa Electroni..
  • Contact:Ruixinmslong
  • Tel:86-755-61333812
  • Fax:0755-61333820
  • Email: lulu.889@163.com
SIE503.3LT POWER-ONE    07+    18 
    HK CHISHING ELECTRONICS CO.,
  • Contact:maggielee
  • Tel:86-755-61303995
  • Fax:86-755-61306028
  • Email: maggielee@zcicgs.com.cn
SIE503.3LT POWER-ONE    747  Original specialTwo-  18 
    Shen Zhen JinShengDa Electroni..
  • Contact:ms
  • Tel:86-755-61333812/813/814/815
  • Fax:86-755-61333820
  • Email: lulu.889@163.com

SIE503.3LT Datasheet
The K6F3216T6M families are fabricated by SAMSUNG's advanced full CMOS process technology. The families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
SIE503.3LT Price

__ -
IIIIII _ AV = +1VN
RL =100 - RF = 430
_ VIN = 20mVp-p
1


SIE503.3LT on stock

-45 -50 -60
Parameter Symbol Min Max Min Max Min Max Units Note
Random read or write cycle time tRC 74 84 1 04 ns
Read-modify-write cycle time tRWC 101 113 1 38 ns
Access time from RAS tRAC 45 50 60 ns 3,4,10
Access time from CAS tCAC 1 2 13 15 ns 3,4,5
Access time from column address tAA 23 25 30 ns 3,10
CAS to output in Low-Z tcLz 3 3 3 ns 3
Output buffer turn-off delay from CAS tc EZ 3 1 3 3 13 3 13 ns 6,13
OE to output in Low-Z tOLZ 3 3 3 ns 3
Transition time (rise and fall) 1 50 1 50 1 50 ns 2
RAS precharge time tR P 25 30 40 ns
RAS pulse width tRAS 45 10K 50 10K 60 10K ns
RAS hold time tRSH 8 8 1 0 ns
CAS hold time tCSH 35 38 40 ns
CAS pulse width tCAS 7 5K 8 10K 1 0 10K ns 1 4
RAS to CAS delay time tRCD 11 33 11 37 14 45 ns 4
RAS to column address delay time tRAD 9 22 9 25 1 2 30 ns 1 0
CAS to RAS precharge time tCRP 5 5 5 ns
Row address set-up time tASR O O 0 ns
Row address hold time tRAH 7 7 1 0 ns
Column address set-up time tASC 0 0 O ns
Column address hold time tCAH 7 7 1 0 ns
Column address to RAS lead time tRAL 23 25 30 ns
Read command set-up time tR CS 0 0 0 ns
Read command hold time referenced to CAS tRCH 0 0 0 ns 8
Read command hold time referenced to RAS tRRH 0 0 0 ns 8
Write command hold time tWCH 7 7 1 0 ns
Write command pulse width tW P 6 7 1 0 ns
Write command to RAS lead time tRWL 8 8 1 0 ns
Write command to CAS lead time tCWL 7 7 1 0 ns
Data set-up time tDS 0 0 0 ns g


N otes 1. For VCC-VEE {min., max.). 50% duty cycle. The supply current (ICC2+ICC3) does not include the load drive current {lccl). Add max. 45 mA for the three outputs. Load is 50 ] into VCC -2V. 2. To maintain good LED reliability, the device should not be held in the ON state for more than the specified time. Normal operation should be done with 50% duty cycle. 3. To achieve proper PECL output levels the 50 ] termination should be done to VCC -2 V. For correct termination see the application notes.