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SIJ Datasheet

State Description
0 3.3V Buffer power off
1 After 3.3V supply is detected to rise above l.8V-2.OV, the buffer enters state l and initiates a 0.2-ms-0.3-ms delay
2[3] Buffer waits for a valid clock on the SRC_IN input and PWRDWN# deassertion
3[2] Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation


SIJ Price

PACKAGE TUBE T&R
TSSOP 74LCX16541TTR


SIJ on stock

II IIIIII I I I I iN = 4.3 lIII
VOUT = 3.3 V I I
COUT = 1 Tj = 25IC
l
1
l J
IOUT-1 mA]
IIII - L
l IU --I
IOU = 50 m