SIK55014F00A200 Datasheet| Parameters | Test Conditions | Pin | Symbol | Min | Typ | Max | Unit | | Oscator | | Frequency | | 4 | f | 10 | | 2000 | Hz | | Threshold cycle Upper Lower | V8=High= V8=Lowa2=!ji | | 1 a2 a3 | 0.68 0.65 0.26 | 0.7 0.67 0.28 | 0.72 0.69 0.3 | | | Oscillator current | VBatt= 12V | | +losc | 34 | 45 | 54 | UA | | Frequency | C4 0pen, C2 = 68 nF duty cycle = 50% | | f | 56 | 75 | 90 | Hz | | | | | | | | |
SIK55014F00A200 Price| CHARACTERISTIC | SYMBOL | PIN | TEST CIR- CUIT | TEST CONDITION | MIN | TYP | MAX | UNIT | | Output Voltage | VREG | VCC | | | 4.75 | 5.0 | 5.25 | V | | Line Regulation | VLINE | VCC | | VIN = 5.540V | | O1 | 0.5 | % | | Load Regulation | VLOAD | VCC | | ILOAD =150mA | | O1 | 0.5 | % | | Temperature Coefficient | | VCC | | | | 0.01 | | % /oC | | Output Voltage | VOL | RESET,M | | IOL=lmA | | | 0.5 | V | | Output Leakage Current | lLEAK | RESET,M | | VOUT=10V | | | 5 | A | | Input Current | IIN | TC | | VIN= 03.5V | -3 | | 3 | A | | | VIH | | | | | VREG ×80% | | V | | Threshold Voltage | VIL | TC | | | | VREG ×40% | | | Input Current | IIN | CK | | VIN= 5V | | 0.14 | 0.3 | mA | | | VIH | | | | 2 | | | V | | Input Voltage | VIL | CK | | | | | 0.5 | | Reset Detect Voltage | | VCC | | | VREG ×85% | VREG ×88% | VREG ×91% | V | | Standby Current | IST | VCC | | VIN =14V | | O6 | 1.2 | mA | | Overvoltage Detection | VSD | BIAS | | | | 44 | | V | | Watchdog Timer | lWD | RESET | | | 0.9× CTRT | 1.1× CTRT | 1.3× CTRT | | | Reset Timer (1) | rRST(1) | RESET | | | 1.3× CTRT | 1.6× CTRT | 1.9× CTRT | | | Reset Timer (2) | rRST (2) | RESET | | | 300× CT | 700× CT | 1500× CT | | | Clock Pulse Width | TW | CK | | | 3 | | | S | | | | | | | | | |
SIK55014F00A200 on stock| No. Parameters | Test Conditions | Pin | Symbol | Min | Typ. | Max | Unit | Type* | | 1.1 | Supply voltage range | | 1 | Vs | 2.7 | | 5.5 | V | A | | 1.2 | Supply Current | VS= 2.7 V | 1 1 | Is Is | 9 3 | | 13 6.2 | mA mA | A A | | 1.3 | Conversion Supply Current | RL = 50 Q, Rr = RL = 50 Q, Rr = 56 Q | 1 | PGc PGc | | 9 4 | | dB dB | B | | 2 | Operating Frequencies | | 2.1 | RF, frequency | | 2 | RF | 10 | | 2500 | MHz | D | | 2.2 | LO, frequency | | 7 | fLO, | 50 | | 2500 | MHz | D | | 2.3 | IFo frequency | | 5 | fIFo | 50 | | 2500 | MHz | D | | 3 | Isolation | | 3.1 | LO spurious at RF, | PiLO = -10 t0 0 dBm | 7.2 | ISLO-RF | | -30 | | dBm | D | | 3.2 | RF, to LO, | PiRF = -25 dBm | 2.7 | ISRF-LO | | 35 | | dB | D | | 3.3 | LO spurious at IFo | PiLO = -10 t0 0 dBm | 5.7 | ISLO-IF | | -25 | | dBm | D | | 3.4 | IFo to LO, | | 5.7 | ISIF-LO | | 30 | | dB | D | | 4 | Output (IF) | | 4.1 | Output compression point | | 5 | CPo | | -10 | | dBm | D | | 5 | Input (RF) | | 5.1 | Input impedance | | 2 | ZRF, | | 700110.8 | | QllpF | D | | 5.2 | Input compression point | | 2 | CP | | -14 | | dBm | D | | 5.3 | 3rd-order input intercept point | | 2 | IIP3 | | 4 | | dBm | D | | 6 | Input (LO) | | 6.1 | LO level | | 7 | PiLO | | 6 | | dBm | D | | 7 | Voltage Standing Wave Ratio (VSWR) | | 7.1 | Input LO | | 7 | VSWRLO, | | <2 | | | D | | 7.2 | Output IF | | 4 | VSWRIFo | | <2 | | | D | | 8 | Noise Performance | | 8.1 | Noise figure | PiLO = 0 dBm, Rr = | | NF | | 10 | | dB | D | | 9 | Power-down Mode | | 9.1 | Supply current | VPU < 0.5V VPU = OV | 1 | ISPU | | <5 | 30 | UA UA | B B | | 10 | Power-down Voltage | | 10.1 "Power ON" | Vs = 3.5 t0 5.5 V Vs = 2.7 t0 3.5 V | 8 | VPON | Vs -0.5 Vq | | Vs + 0.5 Vs + 0.5 | V V | D D | | 10.2 "Power DOWN" | | 8 | VPDN | | | 1 | V | D | | 10.3 Power-down current | Power ON Power DOWN | 8 | IPON IPDN | | 0.15 <5 | 0.22 | mA UA | A D | | 10.4 Settling time | | 5,8 | tsPD | | < 30 | | }~IS | D | | | | | | | | | | |
| | TEST | 2 | DESCRIPTIONi | -135 | -1' | 0 | | | PARAMETER | COND? | MIN | MAX | MIN | MAX | UNITS | | tpdl | A | 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass | | 7.5 | | 10.0 | ns | | tpd2 | A | 2 | Data Propagation Delay | | 10.0 | | 13.0 | ns | | fmax | A | 3 | Clock Frequency with Internal Feedback3 | 137 | | 1 1 1 | | MHz | | fmax (Ext.) | | 4 | Clock Frequency with External Feedback (t 2~t~ | 100 | | 77.0 | | MHz | | fmax (Tog.) | | 5 | Clock Frequency, Max. Toggle | 167 | | 125 | | MHz | | tsul | | 6 | GLB Register Setup Time before Clock, 4 PT Bypass | 4.0 | | 5.5 | | ns | | tcol | A | 7 | GLB Register Clock to Output Delay, ORP Bypass | | 4.5 | | 5.5 | ns | | thl | | 8 | GLB Register Hold Time after Clock, 4 PT Bypass | 0.0 | | 0.0 | | ns | | tsu2 | | 9 | GLB Register Setup Time before Clock | 5.5 | | 7.5 | | ns | | tc02 | | 10 | GLB Register Clock to Output Delay | | 5.5 | | 6.5 | ns | | th2 | | 1 1 | GLB Register Hold Time after Clock | 0.0 | | 0.0 | | ns | | trl | A | 12 | External Reset Pin to Output Delay, ORP Bypass | | 9.0 | | 12.5 | ns | | trwl | | 13 | External Reset Pulse Duration | 5.0 | | 6.5 | | ns | | tptoeen | B | 14 | Input to Output Enable | | 12.0 | | 14.5 | ns | | tptoedis | c | 15 | Input to Output Disable | | 12.0 | | 14.5 | ns | | tgoeen | B | 16 | Global OE Output Enable | | 6.0 | | 7.0 | ns | | tgoedis | c | 17 | Global OE Output Disable | | 6.0 | | 7.0 | ns | | twh | | 18 | External Synchronous Clock Pulse Duration, High | 3.0 | | 4.0 | | ns | | twl | | 19 | External Synchronous Clock Pulse Duration, Low | 3.0 | | 4.0 | | ns | | | | | | | | | |
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