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SIL13114CT176 Datasheet

			Ratings
Symbol	Items	Conditions	Min	Typ.	Max	Unit
IDRM	Repetitive Peak Off-State Current	VAK = VDRM or VRRM ; RGK = 1000 Q Tc = 25 aC Tc = 125 0C			10 200
VTM	Peak On-State Voltage (1)	( ITM =3 A, Peak )		1 2	1 7	V
IGT	Gate Trigger Current (2)	VAK = 6 V, RL=100 Q Tc = 25 aC Tc = - 40 aC			200 500
VGT	Gate Trigger Voltage (2)	VD = 7 V, RL=100 Q Tc = 25 aC Tc = - 40 aC			0 8 1 2	V
VGD	Non-Trigger Gate Voltage (1)	VAK= 12 V, RL=100 Q Tc = 125 0C	0 2			V
dv/dt	Critical Rate of Rise Off-State Voltage	VGM = 0.67VDRM, Exponential waveform , RGK = 1000 Q Tj = 125 0C	200			V/Us
di/dt	Critical Rate of Rise On-State Current	ITM = 3A, lg = 10mA			50	Al,us
IH	Holding Current	VAK = 12 V, Gate Open Tc = 25 aC Tc = - 40 aC		2	5 0 10	mA
RthO_c)	Thermal Impedance	Junction to case			15	oC/w
RthO_a)	Thermal Impedance	Junction to Ambient			125	oc/w

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Pin Number	Pin Name	PWR	1/0	Pin Description
3	XIN		I	Oscillator Buffer Input. Connect to a crystal or to an external clock.
4	XOUT	VDD	O	Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN.
1	FSO/REFO	VDDR	1/0 PU	Power-on Bidirectionallnput/Output. At power-up, FSO is the input. When the power supply voltage crosses the input threshold voltage, FSO state is latched and this pin becomes REFO, buffered copy of signal applied at XIN. (1-2 x strength, selectable by SMBus. Default value is l x strength.)
56	VTTPWRGD#	VDDR	I	If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At power-up, VTT_PWRGD# is an input. When this input transitions to a logic low, the FS (3:0) and MULTSEL are latched and all output clocks are enabled. After the first high to low transition on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the device thereafter. When the VTT_PWRGD# feature is not used, please connect this signal to ground through a 10KI resistor.
56	REF1	VDDR	O	If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C). VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes REFl and is a buffered copy of the signal applied at XIN.
44,42,38, 36,32,30	DDRT (0:5)/SDRAM	VDDD	O	These pins are programmable through strapping pinll, SELSDR_DDR#. If SELSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are "True" copies of signalapplied at Pin45, BUF_IN.ln this mode,VDDD must be 2.5Vlf SeISDR_DDR#.= 1, these pins are configured for SDRAM(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V
43,41,37 35,31,29	DDRC (0:5)/SDRAM	VDDD	O	These pins are programmable through strapping pinll, SELSDR_DDR. If SeISDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are "Complementary" copies of signal applied at Pin45, BUF_IN.ln this mode, VDDD must be 2.5Vlf SeISDR_DDR#.= 1, these pins are configured for SDRAM(1,3,5,7,9,11) single ended clock outputs, copies of(and in phase with) signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V.
7	SELP4_K7/ AGP1	VDDAGP	I/O PU	Power-on Bidirectionallnput/Output. At power-up, SELP4_K7 is the input. When the power supply voltage crosses the input threshold voltage, SELP4_K7 state is latched and this pin becomes AGPl clock output. SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode.
12	MULTSEL/PC12	VDDPCI	1/0 PU	Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. When the powersupply voltage crosses theinput threshold voltage, MULTSEL state is latched and this pin becomes PC12 clock output. MULTSEL = 0, loh is 4 x IREFMULTSEL = 1, loh is 6 x IREF
53	CPUT/CPUOD_T	VDDC	O	3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7.lf SELP4_K7 = 1,this pin is configured as the CPUT Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock Output. See Table 7
52	CPUC/CPUOD_C	VDDC	O	3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7.lf SELP4_K7 = 1, this pin is configured as the CPUC Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock Output. See Table 7
48,49	CPUCS_T/C	VDDI	O	2.5V CPU Clock Outputs for Chipset. See Table 7.
14,15,17,18	PCI (3:6)	VDDPCI	O	PCI Clock Outputs. Are synchronous to CPU clocks. See Table 7
10	FSl/PCI F	VDDPCI	I/O PD	Power-on Bidirectionallnput/Output. At power-up, FSO is the input. When the power supply voltage crosses the input threshold voltage, FSl state is latched and this pin becomes PCI_F clock output.
20	FS3/48M	VDD48M	I/O PD	Power-on Bidirectionallnput/Output. At power-up, FS3 is the input. When the power supply voltage crosses the input threshold voltage, FS3 state is latched and this pin becomes 48M, a USB clock output.

SIL13114CT176 on stock

- V \-i
a			2		f Di
	Z			×	-Cr - 180 0f= 120
		K		1 600	90
j	r	h - 30 l				IT(Av)(A)

PARAMETER	SYMBOL	TEST CONDITION		MIN	TYP.	MAX	UNIT
Detection Voltage	VDET			1.0%		+1.0%	V
Hysteresis Voltage	VHYS			70	90	130	mV
			VDET=1.5V~1.9V Version		0.7	1.5
Quiescent Current	lsS	VDD=VDET+1V	VDET=2.OV-6.OV Version		0.9	2.0
			VDD=1.2V	0.75	2.0
Output Current	IOUT	Nch,VDS=0.5V	VDD=2 4V (>2 7V Version)	4.5	7.0		mA
Output Leak Current	ILEAK	VDD=VOUT=9V				0.1
Detection Voltage Temperature Coefficient	q;VDET lqiTa	Ta=0~+851C			+100		ppm/YC
Delay Time	td	VDD=VDET+1V Cd=4_7nF		8	10	12	ms
Input Voltage of	VMR H			1.5		VDD	V
MR pin (Active "L")	VMR L			0		0.3	V
Input Voltage of	VMR_H			VDD-0.3		VDD	V
MR pin (Active "H")	VMR L			0		VDD-1.5	V
Impedance of MR pin	RMR			1.0	2.0	3O	M l
Operating Voltage ('note 2)	VDD	RL=lOOk1		0.8		9	V