SIL740-560 Datasheet TRACE ON EOF TDMA DREoo DREQ1 ; initialisation SETF /PIACSO /PIACSl /TDTREQ SETF /PIACSO /PIACSl /TDTREQ SETF /PIACSO /PIACSl /TDTREQ SETF /PIACSO /PIACSl /TDTREQ SETF /PIACSO /PIACSl /TDTREQ SETF /PIACSO /PIACSl /TDTREQ SETF /PIACSO /PIAC51 /TDTREQ SIL740-560 Price| Ratings | Symbol | CM200TU-12H | U nits | | Junction Temperature | Tj | -40 t0 150 | 1C | | Storage Temperature | Tstg | -40 t0 125 | ][c | | Collector-Emitter Voltage (G-E SHORT) | VCES | 600 | Volts | | Gate-Emitter Voltage (C-E SHORT) | VGES | +20 | Volts | | Collector Current (Tc = 25IC) | lc | 200 | Amperes | | | | |
SIL740-560 on stock| Errata Number | Document UDdate | Applies to Mask | | ED26 | Description (added 11 6/ 99): The specification DMA Chapter is wrong. "Due to the DSP56300 Core pip eline, after DE bit in DCRx is set, the corresp onding DTDx bit in DSTR will be cleared only after two instruction cycles." Should be replaced with: "Due to the DSP56300 Core pip eline, after DE bit in DCRx is set, the corresp onding DTDx bit in DSTR will be cleared only after three instruction cycles." | 2K30A | | ED27 | Description (added l/12/99): The PBGA mechanical package drawing in the 56301 and 56305 data sheets is incorrect. The figure numbers ofthe incorrect drawings are Figure 3-6 for the 56301 and Figure 3-3 for the 56305. The only incorrect part is the bottom view above the label "VIEW M-M." This view erroneously shows the number of pins on the package to be 256, but the actual number of pins is 252. In the drawing, the four balls in the corners should not appear. Pertains to: Data sheet. To get the art, call Gordon Fowkes and ask. | 2K30A | | | |
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