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The preferred method of synchronizing data access to and from the Watchdog Timekeeper is to access the Command Register by doing a write cycle to address location OB and setting the TE bit (Transfer Enable bit) to a logic 0. This will freeze the external time of day registers at the present recorded time allowing access to occur without danger of simultaneous update. When the watch registers have been read or written a second write cycle to location OB, setting the TE bit to a logic l, will put the time of day registers back to being updated every 0.01 second. No time is lost in the real time clock because the internal copy of the time of day register buffers are continually incremented while the external memory registers are frozen. An alternate method of reading and writing the time of day registers is to ignore synchronization. However, any single read may give erroneous data as the real time clock may be in the process of updating the external memory registers as data is being read.