| SYMBOL | PARAMETER | MIN | TYP. | MAX | UN |
| VDDD | supply voltage digital part | 4.5 | 5 | 5.5 | V |
| VDDA | supply voltage analog part | 4.75 | 5 | 5.25 | V |
| IDD | total supply current | | tbf | | mA |
| VIL | input voltage LOW on YUV-bus | -0.5 | | 0.8 | V |
| VIH | input voltage HIGH on YUV-bus | 2 | · VDDD+0.5 | V |
| fLLC | input data rate | | | 30 | MHz |
| Vo Y,CD | output signal Y, +(R-Y) and t(B-Y) (peak-to-peak value) | | 2 | | V |
| RL Y,CD | output load resistance | 125 | | | Q |
| ILE | DC integral linearity error in output signal (8-bit data) | | | 1 | LSB |
| DLE | DC differential error in output signal (8-bit data) | | | 0.5 | LSB |
| Tamb | operating ambient temperature range | 0 | | 70 | oC |
| | | | | |
A read cycle is executed by setting IW at a high level while /S1 and S2 are in an active state(/S1=L", S2="H"). When setting /S1 at a high level or S2 at a low level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as Icc3 0r Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.