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SIOV-S07K140GS2 SIOV-S07K140GS2 SIOVS07K140GS2 Datasheet

Periodic reference signal output selectable: 1024 Hz, or l second, 1 minute or l hour intervals Data bus is 4-bit bidirectional, with memory-type reads and writes. CMOS device, for very low power consumption, and long battery back-up period. Compatible at pin and function levels with the MSM58321 RS.
SIOV-S07K140GS2 SIOV-S07K140GS2 SIOVS07K140GS2 Price

0.01 0.1 0.3 0.5 0.8 1 1.8 2.4 3	0.009 0.012 0.027 0.039 0.049 0.046 0.054 0.147 0.24	17.9 43.5 55.8 52.5 33.7 22.2 -135.4 179.9 152.1	3.94 3.95 3.93 3.89 3.79 3.69 3.13 2.63 2.19	179.2 174.4 163.4 152.2 135.8 124.9 84.1 57.6 35.7	0.131 0.131 0.133 0.136 0.142 0.149 0.181 0.205 0.225	0.2 1.7 4.8 7.8 11.7 13.8 16.6 14.7 11.6	0.208 0.207 0.204 0.201 0.194 0.191 0.183 0.182 0.184	-0.5 -6.2 -19.1 -31.9 -51.3 -64.2 -106.8 -124.9 -134.9

SIOV-S07K140GS2 SIOV-S07K140GS2 SIOVS07K140GS2 on stock

Parameter	Description	Test Conditions	Max	Unit
CIN	Input Capacitance	TA = 25IC, f = 1 MHz,	10	pF
COUT	Output Capacitance	VDD = 3.3V	10	pF

Programmable Hardware Write Protection The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the Programmable Hardware Write Protect feature. Hardware Write Protection is enabled when WP pin is LOW, and the WPEN bit is "1". Hardware Write Protection is disabled when either the WP pin is HIGH or the WPEN bit is "0". When the chip is hard- ware write protected, nonvolatile writes are disabled to the Status Register, including the Block Lock bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written.

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