| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
SIP825ZEU Datasheet
SIP825ZEU Price
SIP825ZEU on stock Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.OV for periods of less than 20 ns Maximum DC voltage on output pins is Vcc +0.5V, which may overshoot to Vcc +2.OV for periods of less than 20 ns. (2) Latch-up protection is provided for stresses up t0 100 mA on address and data pins from -1V to Vcc +1V. STATUS LINES (pins 23, 24) These lines indicate the present state of the ADC. After a data request has been received and the current integration cycle is complete, the ADC will output the data collected subsequent to the previous data request. Si will go to logic l to acknowledge the data request. The 8 bytes of data will be placed on the data bus sequentially. A logic 1 0n So indicates valid data on the data bus. After the data has been transmitted, Si will return to logic 0. |
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