| lSymbol | Parameter | Value | Unit l |
| lTjDIS | Thermal disable junction temperature threshold | 160 t0 190 | l |
| lRtrij_pins | Thermal resistance junction to pins | 14 | 1C/W l |
| | | |
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level o or l. VOS refers to the common-mode of OUTp and OUTN. Output capacitance inside the device, from either OUTp or OUTN to ground. Refer to the LVDS application note (SBAA118) for a description of data setup and hold times. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins.
