| Name | Function |
| AO-A17 Address Input | These 18 address inputs select one of the 262,144 x 8-bit words in the RAM |
| CEl Chip Enable l Input CE2 Chip Enable 2 Input | CEl is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. |
| WE Write Enable Input | The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memor\t location. |
| OE Output Enable Input | The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. |
| DQO-DQ7 Data Input/Output Ports | These 8 bi-directional ports are used to read data from or write data into the RAM. |
| Vcc | Power Supply |
| Gnd | Ground |
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