The HDLC Protocol Controller provides two separate signals TEOP & REOP indicating the end of packet transmitted and received respectively. TEOP is a HIGH going pulse for one bit duration asserted during the last bit of the closing flag or Abort sequence of the transmit packet. REOP is also a HIGH going pulse occurring for one bit period when a closing flag is received or an incoming packet is aborted or an invalid packet of 24 0r more bits is detected. However, REOP is not generated for invalid packets of length less than 24 bits. These 'end of packet' signals are useful in multiplexing several data links on to a single HDLC Protocol Controller.
This frequency-to-voltage converter operates by averaging (filtering) the reference current pulses triggered on every falling edge at the frequency input. Voltage ripple with a frequency equal to the input will be present in the output voltage. The magnitude of this ripple voltage is inversely proportional to the integrator capacitor. The ripple can be made arbitrarily small with a large capacitor, but at the sacrifice of settling time. The R-C time constant of CINT and Rrw determine the settling behavior. A better compromise between output ripple and settling time can be achieved by adding a low-pass filter following the voltage output.
