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ST92F124JV9TB Datasheet

Note: 1. Commands not interpreted in this table will default to read array mode. 2. A wait of 10ps is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation. 3. X = Don't Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com- mand cycles. 5. Signature Address bits AO, A1, at VIL will output Manufacturer code (20h). Address bits AO at VIH and Al , at VIL will output Device code. 6. For Coded cycles address inputs A11-A16 are don't care. 7. Read Data Polling, Toggle bits until Erase completes.
ST92F124JV9TB Price

The CAT28C64A/CAT28C64AI is manufactured using Catalyst's advanced CMOS floating gate technology. It is designedto endure 10,000 progralTr/erase cycles and has a data retention of l O years. The device is available in JEDEC approved 28 pin DIP and SO or 32 pin PLCC packages.
ST92F124JV9TB on stock

PARAMETER	SYMBOL MIN.	TYP	MA×	UNIT CONDITIONS.
Collector-Base Breakdown Voltage	V(BR)CBO -40	-55		V IC_-lOOccA
Collector-Emitter Breakdown Voltag	V(BR)CER -40	-55		V IC=-lccA, RB " 1K j
Collector-Emitter Breakdown Voltage	V(BR)CEO -20	-30		Vlc--lOmA*
Emitter-Base Breakdown Voltage	V(BR)EBO 6	8		V lr-lOOccA
Collector Cut-Off Current	ICBO		-50 1	nA VCB--30V VCB--30V,TamtrlOOoC
Collector Cut-Off Current	ICER R "1K		-50 1	nA VCB--30V ccA VCEr--30V, TamrrlOOoC
Emitter Cut-Off Current	IEBO		-10	nA VEB--6V
Collector-Emitter Saturation Voltage	VCE(sat;	-45 -90 -180 -230	-100 -150 -250 -310	mV lc--0.5A, IB--lOmA* mV lc--2A, IB=-200mA* mV lc--4A, IB--400mA* mV lc--5A, IB=-300mA*
Base-Emitter Saturation Voltage	VBE(sat;	-960	-1100	mV lc--5A, IB--300mA*

TEST PROCEDURES AND REQUIREMENTS
TEST		PROCEDURE	REQUIREMENTS
NAME OF TEST	REFERENCE	(quick reference)	REQUIREMENTS
Mounting	IEC 60384-18, subclause 4.3	shall be performed prior to tests mentioned below; reflow soldering; for maximum temperature load refer to chapter "Mounting"	AC/C: +5% tan 8 i spec. limit IL2 i spec. limit
Endurance	IEC 60384-18/ CECC 32 300, subclause 4.15	Tamb = 125 0C; UR applied; 1000 hours	UR - 6.3 V; AC/C: +15% UR > 10 V; AC/C: +lO% tan 8 i 2 x spec. limit IL2 i spec. limit
Useful life	CECC 30301, subclause l .8.1	Tamb = 125 0C; UR and IR applied; 1 500 hours	AC/C: +50% tan 8 i 3 x spec. limit IL2 i spec. limit no short or open circuit total failure percentage: i 1%
Shelf life (storage at high temperature)	IEC 60384-18/ CECC 32 300, subclause 4.17	Tamb = 125 0C; no voltage applied; 1000 hours after test: UR to be applied for 30 minutes, 24 t0 48 hours before measurement	for requirements see 'Endurance test' above
Reverse voltage	IEC 60384-18/ CECC 32 300, subclause 4.16	Tamb = 125 0C: 125 hours at U = -0.5 V, followed by 125 hours at UR	AC/C: +15% tan 8 i 1.5 x spec. limit IL2 i spec. limit

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