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ST92F124V9QC Datasheet

VOH Logic l High Input Voltage 2.4 V
VIL Logic o Low Input Voltage 0.8 V
IIN Input Current OV " VIN " VDD 1 1


ST92F124V9QC Price

]L·-y 2SB0792 VCEO IC = -100 UA,IB = 0 -150 V
fB 2SB0792A -185
-y·(C) VEBO IE = -10 LiA, Ic = 0 -5 V
]L·(E) ICBO VCB = -100 V, IE = 0 -1 yA
4 2SB0792 hFE VCE = -5 V,IC = -10 mA 130 450
2SB0792A 130 330
]L·-y VCE(,zu) Ic = -30 mA, IB = -3 mA -1 V
7 fr VCB = -10 V,IE = 10 mA, f= 200 MHz 200 MHz
]Lf Cob VCB = -10 V, IE = O, f'= 1 MHz 4 pF
NV VCE = -10 V,IC = -1 mA, Gv = 80 dB Rg = 100 kQ, Function = FLAT 150 mV


ST92F124V9QC on stock
. 4ns typ. propagation delay . SV t0 12V input supply . +2.7V to +5V output supply . True-to-ground input . Rail-to-rail outputs . Separate analog and digital supplies . Active low latch . Dual available (EL5285C) . Window comparator (EL5287C) . Quad available (EL5485C & EL5486C) . Pin-compatible 6ns family available (EL5x81C, EL5283C & EL5482C)

Pin No. Pin Name Applied Voltage (v) Pin Voltage (v) Function and Explanation Equivalent Circuit
1 IFinput 1.2 This pin is the IF input pin to the double balanced mixer (DBM). The input is designed as a high impedance. The circuit helps suppress spurious signals. Also this symmetrical circuit can keep
specified performance insensitive to process- r
condition distribution. For that reason, a double balanced mixer is adopted. Lo U
2 4 GND GND GND pin. Ground pattern on the board should be formed as wide as possible. Track length should JL
be kept as short as possible to minimize ground inductance. 6= =H
3 LOinput 2.1 Local input pin. Recommended input level is -10 t0 0 dBm.
5 Vcc 2.7 t0 3.3 Supply voltage pin. =
6 RFoutput Same bias as Vcc through external inductor This pin is the RF output from the double balanced mixer. This pin is designed as an open collector. Due to the high impedance output, this pin should be externally equipped with an LC matching circuit to the next stage.