| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
ST92F250JV2TB Datasheet
ST92F250JV2TB Price Wide supply voltage range from l.65 V t0 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V t0 1.95 V) x JESD8-5 (2.3 V t0 2.7 V) x JESD8-B/JESD36 (2.7 V t0 3.6 V). ESD protection: x HBM El/VJESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. +24 mA output drive at Vcc = 3.0 V CMOS low power consumption Latch-up performance exceeds 250 mA Multiple package options Specified from -40 IC to +85 IC and from -40 IC to +125 IC ST92F250JV2TB on stock the TVS clamping voltage and the voltage due to the parasitic inductance (VC(TOD = Vc + L di/dt) . Parasitic inductance in the protection path can result in signifi- cant voltage overshoot, reducing the effectiveness of the suppression circuit. An ESD induced transient for example reaches a peak in approximately lns. For a 30A pulse (per IEC 61000-4-2 Level 4), 1nH of series inductance will increase the effective clamping voltage by 30V (V = 1x10g (30/1x10 g. For maximum effectiveness, the following board layout guidelines are recom- mended: Grounding The input and output sections are fully floating from each other. They may be operated separately or with a common ground. If the input and output sections are connected either directly at the converter or at some remote location from the converterit is suggested that a 3.3 t0 10pF, 0.5 t0 5 0hm ESR capacitor bypass be used directly at the converteroutput pins. This capacitorpreventsanycommon modeswitching currents from showing up at the converter's output as normal mode output noise. Do not use the lowest ESR, biggest value capacitor that you can find! This can only lead to reduced system performance or oscillation. See our application note "Understanding Outputlmpedance For Optimum Decoupling" for more information. |
