The interrupt mask registers (IMRA and IMRB) may be used to block a channel from making an interrupt request. Writing a zero into the corresponding bit of the mask register will still allow the channel to re- ceive an interrupt and latch it into its pending bit (if that channel is enabled), but will prevent that chan- nel from making an interru pt request. Ifthat channel is causing an interrupt request at the time the cor- responding bitin the mask register is cleared, the re- quest will cease. If no other channel is making a re- quest, INTR will go inactive. If the mask bit is re-en- abled, any pending interrupt is now free to resume its request unless blocked by a higher prionty re- quest for se rvice. IM RAand IMRB are also readable A conceptual circuit of an interrupt channel is shown in figure 10.
| PARAMETER | MIN | TYP | MAX | UNIT |
| D package RejA Junctiontofreeairthermalresistance SL Package | | | 165 115 | oc/W |
| | | | |
