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ST95010CM1TR Datasheet

PIN NUMBER	SYMBOL	FUNCTION
1	FGND	Frame Ground
2	Vss	Power Supply (GND)
3	Vdd	Power Supply (+ 5V)
4	Vo	Contrast Adjustment
5	R/W	Data Read/Write
6	E	Enable Signal
7	CS	Chip Select
8	RS	Data Instruction Select
9	NC	No Connection
10	RST	Reset Signal
11	DBO	H/L Data Bus Line
12	DB1	H/L Data Bus Line
13	DB2	H/L Data Bus Line
14	DB3	H/L Data Bus Line
15	DB4	H/L Data Bus Line
16	DB5	H/L Data Bus Line
17	DB6	H/L Data Bus Line
18	DB7	H/L Data Bus Line
19	NC	No Connection
20	NCNee	NC/Negative Voltage Output

ST95010CM1TR Price

* All specs and applications shown above subject to change without prior notice. 7 AN KAN RD LU~HU TAOYUAN TA~WAN RO~Erra~server@ceramate.com.tw Tel:886- 3-352 9445 H ttp: www.cera m ate.com.tw Fax:886 -3-3521052 Page 8 0f 19 Rev l.2 May 6,2002
ST95010CM1TR on stock

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The delay line associated with the second PLL precisely centers the data transitions within the data window. The de- lay line remains accurate independent of temperature, pow- er supply, lC process variation or external components. The design also ensures that the charge pump up and down circuits both produce an active pulse at each zero phase crossing when in lock to guarantee a linear phase detector gain characteristic.

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