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ST95010WM6 Datasheet

SIGNAL	PIN NAME
OE	Output Enable input
Vcc	Power supply (+5 V)
GND	Ground

ST95010WM6 Price

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP.	MAX	UNIT
IDC!	quiescent current (pin 2)	PD=0 rriW		280	320	mA
PldB	load power	at l dB gain compression	13	17		W
Gp	power gain		27	29	31	dB
CGp freq	gain flatness over frequency range			0.2	1	dB
CGp pwr	gain flatness over power band	PL = 25 mW up t0 2.5 W	-0.8	-0.2	+0.2	dB
GOB	out of band gain	small signal, PD = 0 dBm; f< 920 MHz, f > 960 MHz			GPimax + 1 note 1	dB
VSWRin	input VSWR			1.61	21
IMD	reverse intermodulation	fi = fe +100 kHz Pcarrier = 2.5 W; Pinterference = -40 dBc;		-66	-60	dBc
H2	second harmonic			-38	-35	dBc
H3	third harmonic			-61	-58	dBc
	stability	VSWR " 3 : 1 through all phases; VS2 = 25 t0 28 V	all spurious outputs more than 60 dB below desired signal
	ruggedness	VSWR = 10 : 1 through all phases; PL = 5 W	no degradation in output power
EDGE (PL = 2.5 W average)
T1	efficiency		12	15		%
SR200	spectral regrowth;	200 kHz		-36	-35	dBc
SR400	EDGE GSM signal	400 kHz		-65	-63	dBc
EVMrms	rms EDGE signal distortion			0.4	1.2	%
EVMM	peak EDGE signal distortion			1.2	4	%
Intermodulation distortion (PL = 2.5 W average)
d3	third order intermodulation	carrier spacing = 200 kHz		-45	-40	dBc
ds	fifth order intermodulation			-52		dBc
d7	seventh orderintermodulation			-60		dBc

ST95010WM6 on stock

NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Internal TCSR can be supported(ln commercial Temp : Max 400C/Max 700C) 4. K4S513233F-M(E)C" 5. K4S513233F-M(E)L" 6. K4S513233F-M(E)F" 7. Unless otherwise noted, input swing level is CMOS(VIH NIL=VDDQNSSQ).

TL/D/10329-4 Note: All times shown in parentheses are minimum and in ys unless otherwise specified. Note l: National's standard product warranty applies only to devices programmed to specifications described herein. Note 2: Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp The 27C16 must not be inserted into or removed from a board with Vpp at 25V +1V to prevent damage to the device. Note 3: The maximum allowable voltage which may be applied to the Vpp pin during programming is 26V. Care must be taken when switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification. A 0.1 yF capacitor is required across Vpp, vcc to GND to suppress spurious voltage transients which may damage the device.

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