| Table 29. External Timing Parameters |
| Symbol | Parameter | Conditions |
| tDRR | Register-to-register delay via four LEs, three row interconnects, and fou r local interconnects | (8) |
| tINSU | Setup time with global clock at IOE register | (9) |
| tINH | Hold time with global clock at IOE register | (g) |
| 0UTCO | Clock-to-output delay with global clock at IOE register | (g) |
| tPCISU | Setup time with global clock for registers used in PCI designs | (9)( 10) |
| tPCIH | Hold time with global clock for registers used in PCI designs | (9)(1 0) |
| tPCICO | Clock-to-output delay with global clock for registers used in PCI designs | (9)(1 0) |
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