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STC89LE52AD-90C-PI-NJ-PQJ Datasheet

PIN	DESCRIPTION
1	GND
2	RF in
3	GND
4	VS+RFout

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TOGGLE BIT: In addition to Data Polling the AT49BV802A(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, suc- cessive attempts to read data from the memory will result in l/06 toggling between one and zero. Once the program cycle has completed, 1/06 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see "Sta- tus Bit Table" on page 10 for more details.
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	0 7		+		I I IIII 1 0!is
	1				1 00rus ims
					10ms
l1


	D.C. OI	'ERATIO		U	Tj=150'C Tc=25'C
					Single pulse
2 4 68 2 4 68 2 4 68 r)_l in o in'I o .				022 4 68 VDS (V:

Features 128K x 16-bit organization EDO Page Mode for a sustained data rate of 67 MHz RAS access time: 40, 45, 50, 60 ns Dual CAS Inputs Low Power Dissipation Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh Refresh Interval: 512 cycles/8ms Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages Single +5V + 10% Power Supply TTL Interface

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