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STD9NM60-1 Datasheet
Each input port of the AD6636 has its own clock used for latching onto the input data, but Input Port A clock (CLKA) is used also as the input for an on-board PLL clock multiplier. The output of the PLL clock is used for processing all filters and processing blocks beyond the data router following CIC filter. The PLL clock can be programmed to have a maximum clock rate of 200 MHz.
STD9NM60-1 Price
-_-~- Ch8f8Ctir18tICs . Materiat tested to UL 94 V2. . Jack screws: galvanlaad 8tael (other coatlngs a\ndlabb upon request). * Strain rd~t provtded by heat recoveraWe adhaNa coted ring. . Standard coiour: black {other colours availabio upon request). -_-----_- ---__'-~--_-_-- [,'( Llh, Tneoi can be supp~ieo dther with a t\eat shnnkabte cable outlet whlch will accspt cable ot 6 mm t0 11 mm dianwtar ~ E wrslon or with tha cable autlert oxp&wteo to the requird cable dlameter - D varston The D version doei not require shrinking orrto tha cabto and tho boot 19 rermwab~ -~-----_---_'-'-~--__-'- -~--N~~---- -~---_-_------ For th E wrsion tha rocommendad heaung tool Is a. Raycham CV 6302 (800 W) or CV 1081 (1,400 W - industriai purpose) fHwd wlth a 202-P-ADPl adaptor. [T IW_ Cv P8cknol~w Standard pack Mlnlmum ordNrCu"..tFtv _ :. vt,rbiU" iUu preces - filb piecBs D wrsion l,000 ploct}a t,000 pieces N-_-N__ sion I- I. j,:,3jr;2:aileoutls'o' Part nombortrW sy8t*m ). I T:9 Connector R{ZX 9, 15, 25 and 37 I P uctgnwpdoscrlptlon
STD9NM60-1 on stock
1 Write is executed when both CE and WE are at low simultaneously. :f:Z Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. *3 tWRl iS tested from the rising edge of CE, until the end of the write cycle.

Symbol Test Condition Max Units Condition
Cl/0 Input/Output Capacitance (SDA) 8 pF Vu0 2 0V
CIN Input Capacitance (AO, A1, A2, SCL) 6 pF VIN= OV