| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| STH11N60S5 | ID | 414 |
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STH11N60S5 Datasheet
STH11N60S5 Price
STH11N60S5 on stock During a fault, CT charges at a rate determined by the internal charging current and the external timing capacitor. Once CT charges t0 2.5 V, the fault comparator switches and sets the fault latch. Setting of the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with the 1GA current source, 12, until 0.5 V is reached. Once the voltage at CT reaches 0.5 V, the fault latch resets, which re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the fault comparator closes the charging switch causing the cycle to begin. Under a constant fault, the duty cycle is given by: The unit of data transmission is 8 bits. By turning the SDA line "L," the slave device mounted on the system bus which receives the data during the 9th clock cycle outputs the acknowledgment signal verifying the data reception. When the EEPROM is rewriting, the device does not output the acknowledgment signal. |
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