When the IDLE n instruction is used, it slows the processor's internal clock and thus its response time to incoming interrupts the l-cycle response time ofthe standard IDLE state is in- creased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21xx will remain in the IDLE state for up to a maximum ofn CLKIN cycles (where n = 16, 32, 64, or 128) before resuming normal operation.
STK10C68-LF25I on stock| D0-41 |
| f l | |
| f | L |
| { l | | _JMark L |
| | C |
| | DIMENSIONS | |
| | INCHES | MM | |
| DIM | MIN | MAX | MIN | MAX | NOTE |
| A | 0 1 60 | 0 205 | 4 1 0 | 5 20 | |
| B | 0 080 | 0 1 07 | 2 00 | 2 70 | Diameter |
| D | 0 028 1 000 | 0 034 | 0 71 25 40 | 0 86 | Diameter |
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| | | | | | | | | |
| TM2 | TMi | IEB | IEA | PC2 | PC1 | PB | PA | I - LIJyIV O = Logic |
| | | | | l }! nr |
| DEFIlES PCO_s [- (. ENABLE PORTA |
| ;hITERRUPT EVIABLE PORT B |
| | INERRUPT - - DO= NOP DO NOT AFFECT COUN OPERATION oi= STOP.I\IOPIFTlMERHAsNO' STOP COUNTING lF THE TIME lO= STOPAFTERTC-STOPIMME[ AFTER PRE5ENTTCIS REACHE |
| | IF TlrVIER HAS NOT STARTED 11= START.LOADMODEANDCC AND5TARTIMMEDIATELYAI LOADING (iF TIWIER l5 NOT PF RUNNING). IF TIMERI5 RUNN lMMEDIATELY AFTER PRE5Eh TCIS REACHED |
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