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STK11C68-LF45I Datasheet

PARITYI	# of "High"s in PDl[15:0]	PARIERRO
High	Even	High
High	Odd	Low
Low	Even	Low
Low	Odd	High

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Symbol	Level	1/0	Function
Vss			ov	Ground electrical potential
VDD			5.OV	Power voltage
V			3.0~5.OV (VDo~Vo)	LCD drive voltage set termination VDD> Vo> Vss
Rs	H/L	l	Resistor select signal o : Instruction resistor (Write) Busy flag address counter (Read) 1 : Data resistor (Read / Write)
R/W	H/L	l	Read (R) Write (W) Select signal o : Write MPU} LCD module 1 : Read MPU LCD module
E	H H/L	l	Signal to start read or write data
DB4 DB7	H/L	1/0	Upper level 4 line data bus Also DB7 is enable to use as busy flag
DBO DB3	H/L	1/0	Lower level 4 line data bus These pins are not used during 4-bits operation

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PARAMETER	TEST CONDITIONS		vCC	MIN TYP(i) MAX	UNIT
	IOH= -100		1.65V t0 3.6V	Vcc - 0.2	V
	IOH= -4 mA		1.65V	1.2
	IOH= -8 mA		2.3 V	1.7
VOH			2.7 V	2.2
	IOH= -12 mA		3V	2.4
	IOH= -24 mA		3V	2.2
	IOL= 100A		1.65V t0 3.6V	0.2	V
	IOL=4 mA		1.65V	0 45
VOL	IOL=8 mA		2.3 V	0.7
	IOL= 12 mA		2.7 V	0.4
	IOL= 24 mA		3V	0 55
lI	VI=0 t0 5.5 V		3.6 V	+5
Io	Vi or Vo = 5.5 V		O	+10	c
10z	VO=0t0 5.5V		3.6 V	+10
	VI = Vcc or GND			20
lcc	3.6 V " Vi " 5.5 V(2)	10=0	3.6 V	20
Clcc	One input at Vcc - 0.6 V, Other inputs at Vcc or GND		2.7V t0 3.6V	500
cI	VI = Vcc or GND		3.3 V	5.5	pF
co	VO = Vcc or GND		3.3 V	6	pF

Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.

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