STK11C68-S45I Datasheet| Ideal O Degrees | Nominal O Degrees | Ideal O Degrees | Nominal O Degrees | Ideal O Degrees | Nominal O Degrees | Ideal O Degrees | Nominal O Degrees | Ideal O Degrees | Nominal O Degrees | Ideal O Degrees | Nominal O Degrees | | O | 0 | 17 | 17.98 | 34 | 33.04 | 75 | 74.00 | 160 | 159.14 | 245 | 244 63 | | 1 | 1 09 | 18 | 18.96 | 35 | 34.00 | 80 | 79.16 | 165 | 164.00 | 250 | 249 14 | | 2 | 2 19 | 19 | 19.92 | 36 | 35.00 | 85 | 84.53 | 170 | 169.16 | 255 | 254 00 | | 3 | 3 29 | 20 | 20.86 | 37 | 36.04 | 90 | 90.00 | 175 | 174.33 | 260 | 259 16 | | 4 | 4 38 | 21 | 21.79 | 38 | 37.11 | 95 | 95.47 | 180 | 180.00 | 265 | 264 53 | | 5 | 5 47 | 22 | 22.71 | 39 | 38.21 | 100 | 100 84 | 185 | 185.47 | 270 | 270 00 | | 6 | 6 56 | 23 | 23.61 | 40 | 39.32 | 105 | 106 00 | 190 | 190.84 | 275 | 275 47 | | 7 | 7 64 | 24 | 24.50 | 41 | 40.45 | 110 | 110.86 | 195 | 196.00 | 280 | 280 84 | | 8 | 8 72 | 25 | 25.37 | 42 | 41.59 | 115 | 115.37 | 200 | 200.86 | 285 | 286 00 | | 9 | 9 78 | 26 | 26.23 | 43 | 42.73 | 120 | 119.56 | 205 | 205.37 | 290 | 290 86 | | 10 | 10.84 | 27 | 27.07 | 44 | 43.88 | 125 | 124 00 | 210 | 209.56 | 295 | 295 37 | | 11 | 11 90 | 28 | 27.79 | 45 | 45.00 | 130 | 129 32 | 215 | 214.00 | 300 | 299 21 | | 12 | 12.94 | 29 | 28.73 | 50 | 50.68 | 135 | 135 00 | 220 | 219.32 | 305 | 303 02 | | 13 | 13.97 | 30 | 29.56 | 55 | 56.00 | 140 | 140 68 | 225 | 225.00 | | | | 14 | 14.99 | 31 | 30.39 | 60 | 60.44 | 145 | 146 00 | 230 | 230.58 | | | | 15 | 16.00 | 32 | 31.24 | 65 | 64.63 | 150 | 150 44 | 235 | 236.00 | | | | 16 | 17.00 | 33 | 32.12 | 70 | 69.14 | 155 | 154 63 | 240 | 240.44 | | | | | | | | | | | | | | | STK11C68-S45I Price Bit 6 0f the Hours Register is defined as the 12- or 24-Hour Select Bit. When set to logic l, the 12-hour format is selected. In the 12-hour format, bit 5 is the AM/ PM bit with logical one being PM. In the 24- hour mode, bit 5 is the second 10-hour bit (20-23 hours). The time of day registers are updated every 0.01 seconds from the real time clock, except when the TE bit (bit 7 0f register B) is set low or the clock oscil ator is not running. STK11C68-S45I on stock| PIN NAME | I/O | FUNCTIONS | LEVEL | | ol t0 080 | Output | LCD drive signal output | VDD to VLC5 | | Dll, D12 | Input | Data signal input | | | El01E102 | I/O | ENABLE signal input/output When S/E = H, this pin is for input. | | SCP | Input | (Shift Clock Pulse) Shift clock pulse input | | FR | Input | (Frame) Frame signal input | VDD to Vss | | LP | Input | (Latch Pulse) Latch pulse signal input | | S/E | Input | Input for mode selection | | DIR | Input | Input data flow direction select | | TEST | Input | Test pin: usually connected to VSS (OV) | | VLC2,3.5 | | Power supply for LCD drive | | | VDD | | Power supply (5V) | | VSS | | Power supply (OV) | | | | |
| | nr | | | wtxclk | ln | 90MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk rising edge. | | wtxdata[15:0] | In | Transmit data bus. | | wtxprty | ln | Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be tied to '0'. | | wtxsoc | In | Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. | | wtxenb | In | Active low transmit data transfer enable. | | wtxclav[0] | Out | Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. | | wtxclav[3:1] (0) | Out | Extra FIFO Full/ Cell buffer available. In MPHY mode and when direct status indication is selected during the Core configuration, one txclav signal is implemented per PHY port. The maximum number of clav signals is limited to fo u r. | | wtxaddr[4:0] | In | Utopia transmit address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. txaddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. | | | | |